In the present invention the terms “memory” and “storage” are used interchangeably and have the same meaning. Consequently compound phrases containing those two terms (like “memory device” and “storage device”, or “memory system” and “storage system”) also have the same meaning.
In the present invention the terms “controlling mechanism” and “controller” are used interchangeably and have the same meaning.
A flash memory system implemented as a Multi-Level Cell (MLC) flash memory is provided for storing more than one bit of data on each memory cell. The writing of data into an MLC flash memory is typically slower than the writing of data into a Single-Level Cell (SLC) flash memory that stores only one bit of data per cell. Therefore, a storage system based on an MLC flash memory might not be capable of recording a stream of incoming data transmitted to it at a higher writing rate.
Typically in cases where data is produced at a rate too high to be directly stored, a cache memory mechanism is provided and designed to operate fast enough to handle the incoming data stream. The cache memory utilizing a second (and faster) memory is implemented between the input data source and the main (and slower) memory of the flash memory device. The input data stream is first written into the faster cache memory, and at a later stage is copied from this faster cache memory into the main memory. As the copying operation between the cache memory and the main memory is typically performed in the background, this operation does not have to meet the strict performance conditions imposed by the input data stream rate, and therefore the lower write performance of the main memory is no longer an obstacle.
However, the implementation of a second memory for caching has its drawbacks. Such implementation requires additional components for the cache memory and its control, whereby complicating the design and management of the memory system.
The prior art include U.S. Pat. No. 5,930,167 to Lee et al., which discloses a memory method and system for caching write operations in a flash memory storage system while achieving the benefits of caching in MLC flash memories but with less of the disadvantages. The MLC flash memory media of the Lee patent is configured to operate as its own cache memory. This is possible since memory cells that store multiple bits can be further implemented to operate similar to SLC memory cells and store only a single bit each, which is an easier task from a technological point of view. As a result, the MLC memory cells can be implemented to achieve the faster write performance characterizing the SLC flash memory. The Lee Patent is incorporated by reference for all purposes as if fully set forth herein.
Known in the art techniques, such as that disclosed in the Lee patent, provide a “built-in” faster cache memory embedded within the MLC flash memory storage system. When data bits are received for storage, they are first written into memory cells that are set to operate in SLC mode. This first writing operation can be done relatively fast. Following this operation, in the background and when time permits it, the data bits are copied from the SLC cells into memory cells that are set to operate in MLC mode. Thus, as the system is designed to employ the higher storage density of the MLC flash memory storage system, the system further handles the faster input stream that could not be handled without the cache memory mechanism.
There are two possible methods for configuring a flash memory system while utilizing such an SLC caching scheme:                A. A dedicated cache method—where a specific portion of the memory cells is always allocated to operate in SLC mode, while other cells are allocated to operate in MLC mode only. In other words, while memory cells operating in SLC mode (SLC cells) and memory cells operating in MLC mode (MLC cells) co-exist within the storage system at the same time, each specific memory cell is either allocated to operate in SLC mode or in MLC mode, and cannot be alternately allocated to operate in SLC mode at one point in time and in MLC mode at another point in time.        B. A mixed cache method—where at least some of the memory cells change modes during the system's operation. That is—a specific memory cell may be allocated to operate in SLC mode at one point in time and utilized for caching data, while at a second point in time the same memory cell may be allocated to operate in MLC mode and utilized for high density data storage in the main memory.        
The dedicated cache method is much simpler to manage in flash memory systems than the mixed cache method. Each portion of the memory cells is pre-allocated to operate either in SLC mode or in MLC mode. Therefore, no real-time mode switching is required. Furthermore, there is no need to provide an information management module for storing and detecting the current operation mode of any memory portion.
The Lee patent discloses a cache implementation that uses the mixed cache method. U.S. patent application Ser. No. 11/318,906 to Lasser discloses a cache implementation that uses the dedicated cache method. The Lasser Application is incorporated by reference for all purposes as if fully set forth herein.
However, both cache implementation methods (i.e. mixed cache method and dedicated cache method) suffer from disadvantages explained herein below. Whenever in this application there is a reference to a cache, it can be either a mixed cache or a dedicated cache.
As explained above, the way a cache memory in a flash memory operates is the following—incoming data is written into the faster-to-write cache storage locations. Later, either when there is idle time or when the cache memory is full and free space must be cleared, the data is read out of the cache memory and written into the slower-to-write main storage locations. After data is copied, the data is no longer needed to be stored in the cache memory and can be deleted so as to make its space available for new incoming data.
The operation of copying data from the cache memory into the main storage area and then clearing the copied area in the cache memory is defined herein as “cache cleaning”. Cache cleaning is typically a relatively time-consuming operation, as this operation includes both the writing of data into the slow-to-write MLC main memory area and the erasing of the copied data from the cache memory area, both operations typically being much slower than reading or even writing data into the SLC cache.
According to known in the art techniques, the cache cleaning is handled automatically and autonomously by the storage device, with the software applications running on the computer hosting the storage device having no control over the timing or any other aspect of the process. The internal controlling mechanism of the storage device determines when there is idle time in which no host computer requests have to be serviced and uses such time for cache cleaning. Additionally, cache cleaning is also initiated by the internal controlling mechanism of the storage device when new data is received from the host computer and there is not enough room in the cache memory for storing the new data. In such case, cache cleaning is applied for making room for the new data in the cache memory.
This way of autonomous cache cleaning causes some disadvantages in certain scenarios of the memory device usage.                A. Consider a scenario where a storage device having an internal cache is used in a portable appliance (such as an audio MP3 player or a video MP4 player). The typical use pattern of the appliance is to download the appliance with a large amount of data and then use the appliance for some period of time only for reading portions of the data. The writing of the data into the appliance is done at a workstation in the office with no time pressure, and the use of the appliance in which portions of the data are read is done in the field upon an instant demand, where the fastest read rate and response time is required.        In such a case, an appliance using a memory device with an internal cache memory operating according to the methods of the prior art might exhibit the following behavior—when downloading the bulk of the data in the office, the cache is filled with data. Once the transfer of the data from the workstation to the appliance is complete, the user disconnects the appliance from the workstation and powers down the appliance. The cache memory is left with a lot of data stored in it, as no cache cleaning can be done without power. At some later time the user takes the appliance to the field and powers the appliance up, using a built-in battery. Once power is up, the internal controlling mechanism of the memory device determines that a lot of data is still stored in the cache memory and starts scheduling cache cleaning operations. Now when the user requests to display some data that has to be read from the memory device, the memory performance is not optimal. A read request received immediately after a cache cleaning operation started, instructs the controlling mechanism either to keep the read request waiting for a while until the cache cleaning operation ends and the memory is not busy any more, or to abort the cache cleaning operation while taking care to preserve the integrity of the data despite the interruption. In both cases the result might be a longer time until the read request is serviced. The average speed of reading data out of the memory device might also suffer, if cache cleaning operations are interleaved by the memory internal controller between the servicing of read requests.        All these undesired effects are really not necessary—as no new data is written into the storage device in such case, no harm would occur if no cache cleaning is to be applied. The cached data could safely remain in the cache memory until a right time is found for cache cleaning, i.e. when such cache cleaning does not interfere with the use of the hosting appliance. However, there is no way in the prior art memory devices to avoid these disadvantages.        B. Consider a scenario where an appliance includes a storage device with an internal cache memory. Assume the cache memory size is 20 Mbytes. The user desires to activate a software application that generates a very large amount of data that is to be stored in the storage device. Assume the amount of data expected to be generated by the application is 15 Mbytes. Also assume the rate of generating data by the application is faster than the write rate of the MLC main storage area but is not faster than the write rate of the SLC cache storage area.        If the user activates the software application when the cache memory is empty, everything will function well: the 15 Mbytes of generated data is transferred into the cache memory at the rate the data are generated, and the cache memory is fast enough to accept all the data. However, in case the user activates the application a second time immediately following the first time, or in case the user turns the appliance power off immediately after activating the application a first time and turns the appliance on again just before a second activation, then approximately 15 Mbytes of data are stored in the cache memory when the second activation starts. The first 5 Mbytes generated by the second activation are handled by the cache memory at the rate of their generation, but then the memory device slows down. For every new chunk of data received in the storage device generated after the first 5 Mbytes, room must first be made. As the process of freeing storage area involves writing data into the main storage area that is assumed to be slower than the data generation rate, the system is not able to cope with the incoming data rate and eventually data is lost.        As in the previous example above, these undesired effects are not really necessary. The user may have agreed to wait with the second activation had he/she known that this is required for a successful activation without any data loss. However, prior art memory devices do not provide any indication about the state of the cache—whether it is empty or full. Additionally, prior art memory devices do not provide any way for a host software application to force an immediate cache cleaning in the memory device.        
Therefore, it is desirable to provide a storage system employing a cache memory, while overcoming the problems resulting from the autonomous operation of the cache controller of prior art techniques.